1. Field of the Disclosure
The invention relates to an exposure mask for manufacturing a semiconductor device and a method of manufacturing a semiconductor device using the same, and more particularly, to an exposure mask capable of increasing depth of focus (DOF) margin of the semiconductor device.
2. Brief Description of Related Technology
As semiconductor devices or integrated circuit devices have become more highly integrated, much research has been devoted to the development of resolution enhancement technology. Resolution enhancement technology can improve the property of a semiconductor device and secure a process margin.
Asymmetry illumination is an example of a resolution improving technology that is introduced into the exposure process. Dipole illumination, for example, can allow the circuit diagram to be implemented in more detail.
In manufacturing a semiconductor device a gate pattern or a wire pattern is formed by performing a photolithography process, in which a photoresist layer is exposed to light using a patterned exposure mask as a mask. The exposure mask is made by forming a light blocking pattern, typically made from Cr, on a transparent substrate, for example, quartz.
In a memory semiconductor device, for example, the device's memory capacity has been largely increased and the critical dimension (CD) of pattern forming the device has been decreased.
Referring to FIG. 1, as a result of a reduction of the size of the gate, a slight change of the focus during the exposure process can cause a the gate to collapse (collapse phenomenon).
Conventionally, an Optical Proximity Correction (OPC) is performed to prevent the collapse phenomenon. Alternatively, an assist feature, as shown in FIGS. 2 and 3, can be used to prevent the collapse phenomenon. The assist feature, however, can be transferred to the semiconductor substrate in the process, causing a more serious problem to occur. The assist feature is formed on the exposure mask to form a main pattern having a desired size. The assist feature is implemented with the size which is not transferred to the semiconductor substrate.
The assist feature does not sufficiently prevent the collapse phenomenon for the change of focus that is required for highly integrated semiconductor devices.
FIG. 2 and FIG. 3 shows the exposure mask of the related art is on one side. A simulation of a pattern to be formed by transferring the exposure mask onto the semiconductor substrate is shown in the other side. The exposure mask is formed by forming an assist feature between gates or between the patterns neighboring the gate. A bar type assist feature is shown in FIG. 2. FIG. 3 shows a dot type assist feature.
The above-described exposure mask and the method of manufacturing a semiconductor device using the same makes higher integration of semiconductor devices difficult because the assist feature does not sufficiently improve the DOF margin.